Functional Verification of Digital Systems

• 26 hrs lectures
• 8 hrs laboratories
• 18 hrs projects

• 60 pts final exam (written part)
• 20 pts labs
• 20 pts projects

A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.

Digital system design, basic programming skills.

• Přednáškové materiály v elektronické formě.

• * Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175. * Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217 * Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141. * Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418. 

1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
3. Introduction to functional verification. Functional verification techniques.
4. Verification methodologies. HVL languages.
5. Pseudo-random stimuli generation, direct tests, constraints.
6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
7. Self-checking mechanisms.
8. Assertions. Assertion languages. Errors reporting.
9. Assertion-based verification.
10. Emulation and prototyping.
11. Hardware debugging.
12. Industry lecture.
13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

1. Creating testbench for arithmetic-logic unit (ALU).
2. Creating verification environment for ALU.
3. Coverage-driven verification of ALU.
4. Assertion-based verification of ALU.

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Labs and project in due dates.