Course details

The Principles of Testable Design Synthesis

PTD Acad. year 2016/2017 Winter semester

Current academic year

The course provides the state-of-the-art coverage in the field of digital systems testing and testable design. It deals with such diagnostic problems which must be solved by a digital circuit designer.

Guarantor

Kotásek Zdeněk, doc. Ing., CSc.

Language of instruction

Czech, English

Completion

Examination (oral)

Time span

  • 39 hrs lectures

Assessment points

  • 100 pts final exam (written part)

Department

Department of Computer Systems (UPSY)

Subject specific learning outcomes and competences

Item has no knowledges.

Learning objectives

Item has no goals.

Prerequisite knowledge and skills

There are no prerequisites

Fundamental literature

  • M. Abramovici, M. A. Breuer, D. Friedman: Digital Systems Testing and Testable Design: Revised Printing, Computer Society Press, 1995, ISBN 0-7803-1062-4, 680 stran
  • A. L. Crouch: Design-for-Test for Digital IC's and Embedded Core Systems, Prentice Hall, 1999, ISBN 0-13-084827-1, 347 stran
  • P. Michel, U. Lauther, P. Duzzy: The Synthesis Approach to Digital System Design, The Kluwer International Series in Engineering and Computer Science, ISBN 0-7923-9199-3, 375 stran

Syllabus of lectures

  • The Principles of Digital System Synthesis, the Implementation of Testability Principles during the Synthesis.
  • The Testability of a Digital Circuit, Controlability and Observability Concepts, Testability Measures.
  • The Evolution of Digital Circuit Testing Methods – the Principles of Increasing Controlability/Observability Parameters of Internal Nodes.
  • Test Points Techniques. The Implementation of Scan Registers to Increase Controlability/Observability
  • Full Scan Methods: Serial Methods (LSSD, Scan Path, Scan Set), Parallel Methods (RAS, ARAS).
  • Partial Scan Methods. The Utilisation of Full and Partial Scan Methods in Synthesis.
  • PLA Testing, Testable PLA Synthesis.
  • Built-in Self Test.
  • Test Pattern Generator, Test Response Analyser.
  • BIST Architectures, Hierarchical Structure of BIST Architectures.
  • CSTP, BILBO.
  • Self-checking design.
  • Boundary Scan. Test of Connections.

Progress assessment

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Controlled instruction

There are no checked study.

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