Result Details

Test Overhead Reduction through RT Level Testability Analysis

HLAVIČKA, J.; KOTÁSEK, Z.; ZBOŘIL, F. Test Overhead Reduction through RT Level Testability Analysis. Proceedings of the IEEE ETW 1997. Cagliary: unknown, 1997. p. 43-47.
Type
conference paper
Language
English
Authors
Hlavička Jan
Kotásek Zdeněk, doc. Ing., CSc.
Zbořil František, doc. Ing., CSc.
Abstract

The paper presents a new method of formal testability analysis made on the RT level in PROLOG environment. This analysis is based on a model which classifies the RT level elements into categories by their function during the testing. The results of the analysis are used for designing a combined test mode in which elements accessible through I-paths are tested with a sequence of parallel test vectors whereas the serial scan method is used only for the remaining elements. This leads to savings both in test application time and in chip area overhead.

Keywords

Design for Testability, RT Level Testability Analysis, RT Level Element Classification, Test Application

Published
1997
Pages
43–47
Proceedings
Proceedings of the IEEE ETW 1997
Conference
IEEE ETW'97 (European Test Workshop)
Publisher
unknown
Place
Cagliary
BibTeX 
@inproceedings{BUT191449,
  author="Jan {Hlavička} and Zdeněk {Kotásek} and František {Zbořil}",
  title="Test Overhead Reduction  through RT Level Testability Analysis",
  booktitle="Proceedings of the IEEE ETW 1997",
  year="1997",
  pages="43--47",
  publisher="unknown",
  address="Cagliary"
}
Projects
Developement of flexible digital architectures, GACR, Standardní projekty, GA102/95/1334, start: 1995-01-01, end: 1997-12-31, completed
Research groups
Intelligent Systems Research Group (RG INTSYS)
Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)
Departments
Faculty of Information Technology (FIT)
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