Result Details
Partial Scan Methodology for RTL Designs
        KOTÁSEK, Z.; ZBOŘIL, F.; HLAVIČKA, J. Partial Scan Methodology for RTL Designs. Compendium of Papers ETW'99. Constance: unknown, 1999. 2 p. ISBN: 0-7695-0390-X.
    
                Type
            
        
                conference paper
            
        
                Language
            
        
                English
            
        
            Authors
            
        
                    Abstract
            
        The paper presents a partial scan design methodology suited for pipelined data paths described at the Register Transfer Level. The methodology can be used for the selection of registers into the partial scan chain.
                Keywords
            
        Partial Scan Methodoly, RTL Design
                Published
            
            
                    1999
                    
                
            
                    Pages
                
            
                        2
                
            
                        Proceedings
                
            
                    Compendium of Papers ETW'99
                
            
                    Conference
                
            
                    ETW'99
                
            
                    ISBN
                
            
                    0-7695-0390-X
                
            
                    Publisher
                
            
                     unknown
                
            
                    Place
                
            
                    Constance
                
            
                    BibTeX
                
            @inproceedings{BUT191434,
  author="Zdeněk {Kotásek} and František {Zbořil} and Jan {Hlavička}",
  title="Partial Scan Methodology for RTL Designs",
  booktitle="Compendium of Papers ETW'99",
  year="1999",
  pages="2",
  publisher="unknown",
  address="Constance",
  isbn="0-7695-0390-X"
}
                
                Projects
            
        
        
            
        
    
    
        Methodology and tools for digital circuits testability analysis, GACR, Standardní projekty, GA102/98/1463, start: 1998-01-01, end: 2006-03-31, completed
            
        
                Research groups
            
        
                Intelligent Systems Research Group (RG INTSYS)
                
Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)
        Supercomputing Technologies Research Group SC@FIT (RG SC@FIT)
                Departments