//===- TableGen'erated file -------------------------------------*- C++ -*-===//
//
// Assembly Writer Source Fragment
//
// Automatically generated file, do not edit!
//
//===----------------------------------------------------------------------===//

/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
void CodasipAsmPrinter::printInstruction(const MachineInstr *MI, raw_ostream &O) {
  static const unsigned OpInfo[] = {
    0U,	// PHI
    0U,	// INLINEASM
    0U,	// PROLOG_LABEL
    0U,	// EH_LABEL
    0U,	// GC_LABEL
    0U,	// KILL
    0U,	// EXTRACT_SUBREG
    0U,	// INSERT_SUBREG
    0U,	// IMPLICIT_DEF
    0U,	// SUBREG_TO_REG
    0U,	// COPY_TO_REGCLASS
    1U,	// DBG_VALUE
    0U,	// REG_SEQUENCE
    0U,	// COPY
    2147483659U,	// CALLEND
    2684354585U,	// CALLSTART
    2147483689U,	// i_2_reg_ops__opc_mov__rmem__rmem__
    2415919152U,	// i_3_reg_ops__opc_and__rmem__rmem__rmem__
    2415919157U,	// i_3_reg_ops__opc_or__rmem__rmem__rmem__
    2181038137U,	// i_3_reg_ops__opc_sll__rmem__rmem__rmem__
    2181038142U,	// i_3_reg_ops__opc_sra__rmem__rmem__rmem__
    2181038147U,	// i_3_reg_ops__opc_srl__rmem__rmem__rmem__
    2415919176U,	// i_3_reg_ops__opc_vadd__rmem__rmem__rmem__
    2415919182U,	// i_3_reg_ops__opc_vmul__rmem__rmem__rmem__
    2181038164U,	// i_3_reg_ops__opc_vsub__rmem__rmem__rmem__
    2415919194U,	// i_3_reg_ops__opc_xor__rmem__rmem__rmem__
    2181038175U,	// i_arithm_imm__opc_addi__rmem__rmem__uimm16__
    2214592607U,	// i_arithm_imm__opc_addi__rmem__rmem__uimm16____SPEC_op0_0
    2181038181U,	// i_arithm_imm__opc_ori__rmem__rmem__uimm16__
    2214592613U,	// i_arithm_imm__opc_ori__rmem__rmem__uimm16____SPEC_op0_0
    2248147045U,	// i_arithm_imm__opc_ori__rmem__rmem__uimm16____SPEC_op0_65535
    2147483754U,	// i_ext__opc_sext32__rmem__rmem__
    2147483762U,	// i_ext__opc_sext8__rmem__rmem__
    2147483769U,	// i_ext__opc_zext16__rmem__rmem__
    2147483777U,	// i_ext__opc_zext8__rmem__rmem__
    2684354696U,	// i_jump_call_imm__opc_call_imm__address26__ES_
    2684354696U,	// i_jump_call_imm__opc_call_imm__address26__GA_
    2684354702U,	// i_jump_call_imm__opc_jump_imm__address26__
    2684354696U,	// i_jump_call_reg__opc_call_reg__rmem__
    2684354702U,	// i_jump_call_reg__opc_jump_reg__rmem__
    2684354702U,	// i_jump_call_reg__opc_jump_reg__rmem___RETURN_CLONE_
    2181038228U,	// i_jump_cond__opc_jumpeq__rmem__rmem__simm16_rel__
    2181038236U,	// i_jump_cond__opc_jumpneq__rmem__rmem__simm16_rel__
    2281701541U,	// i_load_store__opc_load__rmem__rmem__simm16__
    2315255973U,	// i_load_store__opc_load__rmem__rmem__simm16____SPEC_op0_0
    2281701547U,	// i_load_store__opc_store__rmem__rmem__simm16__
    2315255979U,	// i_load_store__opc_store__rmem__rmem__simm16____SPEC_op0_0
    2147483826U,	// i_movhi__opc_movhi__rmem__uimm16__
    3221225650U,	// i_movhi__opc_movhi__rmem__uimm16____SPEC_op0_0
    0U
  };

  const char *AsmStrs = 
    "DBG_VALUE\000#CALLSEQ_END \000#CALLSEQ_START \000VCOPY \000AND \000OR \000"
    "SLL \000SRA \000SRL \000VADD \000VMUL \000VSUB \000XOR \000ADDI \000ORI"
    " \000SEXT16 \000SEXT8 \000ZEXT16 \000ZEXT8 \000CALL \000JUMP \000JUMPEQ"
    " \000JUMPNEQ \000LOAD \000STORE \000MOVHI \000";

  O << "\t";

  // Emit the opcode for the instruction.
  unsigned Bits = OpInfo[MI->getOpcode()];
  assert(Bits != 0 && "Cannot print this instruction.");
  O << AsmStrs+(Bits & 255)-1;


  // Fragment 0 encoded into 1 bits for 2 unique commands.
  if ((Bits >> 31) & 1) {
    // CALLEND, CALLSTART, i_2_reg_ops__opc_mov__rmem__rmem__, i_3_reg_ops__o...
    printOperand(MI, 0, O); 
  } else {
    // DBG_VALUE
    return;
  }


  // Fragment 1 encoded into 2 bits for 3 unique commands.
  switch ((Bits >> 29) & 3) {
  default:   // unreachable.
  case 0:
    // CALLEND, i_2_reg_ops__opc_mov__rmem__rmem__, i_3_reg_ops__opc_and__rme...
    O << ", "; 
    break;
  case 1:
    // CALLSTART, i_jump_call_imm__opc_call_imm__address26__ES_, i_jump_call_...
    return;
    break;
  case 2:
    // i_movhi__opc_movhi__rmem__uimm16____SPEC_op0_0
    O << ", 0"; 
    return;
    break;
  }


  // Fragment 2 encoded into 1 bits for 2 unique commands.
  if ((Bits >> 28) & 1) {
    // i_3_reg_ops__opc_and__rmem__rmem__rmem__, i_3_reg_ops__opc_or__rmem__r...
    printOperand(MI, 2, O); 
    O << ", "; 
    printOperand(MI, 1, O); 
    return;
  } else {
    // CALLEND, i_2_reg_ops__opc_mov__rmem__rmem__, i_3_reg_ops__opc_sll__rme...
    printOperand(MI, 1, O); 
  }


  // Fragment 3 encoded into 3 bits for 6 unique commands.
  switch ((Bits >> 25) & 7) {
  default:   // unreachable.
  case 0:
    // CALLEND, i_2_reg_ops__opc_mov__rmem__rmem__, i_ext__opc_sext32__rmem__...
    return;
    break;
  case 1:
    // i_3_reg_ops__opc_sll__rmem__rmem__rmem__, i_3_reg_ops__opc_sra__rmem__...
    O << ", "; 
    printOperand(MI, 2, O); 
    return;
    break;
  case 2:
    // i_arithm_imm__opc_addi__rmem__rmem__uimm16____SPEC_op0_0, i_arithm_imm...
    O << ", 0"; 
    return;
    break;
  case 3:
    // i_arithm_imm__opc_ori__rmem__rmem__uimm16____SPEC_op0_65535
    O << ", 65535"; 
    return;
    break;
  case 4:
    // i_load_store__opc_load__rmem__rmem__simm16__, i_load_store__opc_store_...
    O << "  +  "; 
    printOperand(MI, 2, O); 
    return;
    break;
  case 5:
    // i_load_store__opc_load__rmem__rmem__simm16____SPEC_op0_0, i_load_store...
    O << "  +  0"; 
    return;
    break;
  }

}


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
const char *CodasipAsmPrinter::getRegisterName(unsigned RegNo) {
  assert(RegNo && RegNo < 9 && "Invalid register number!");

  static const unsigned RegAsmOffset[] = {
    0, 3, 6, 9, 12, 15, 18, 21, 0
  };

  const char *AsmStrs =
    "A0\000A1\000B0\000B1\000C0\000C1\000D0\000D1\000";
  assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
          "Invalid alt name index for register!");
  return AsmStrs+RegAsmOffset[RegNo-1];
}


#ifdef GET_INSTRUCTION_NAME
#undef GET_INSTRUCTION_NAME

/// getInstructionName: This method is automatically generated by tblgen
/// from the instruction set description.  This returns the enum name of the
/// specified instruction.
const char *CodasipAsmPrinter::getInstructionName(unsigned Opcode) {
  assert(Opcode < 49 && "Invalid instruction number!");

  static const unsigned InstAsmOffset[] = {
    0, 4, 14, 27, 36, 45, 50, 65, 79, 92, 106, 123, 133, 146, 
    151, 159, 169, 204, 245, 285, 326, 367, 408, 450, 492, 534, 575, 620, 
    677, 721, 777, 837, 869, 900, 932, 963, 1009, 1055, 1098, 1136, 1174, 1226, 
    1276, 1327, 1372, 1429, 1475, 1533, 1568, 0
  };

  const char *Strs =
    "PHI\000INLINEASM\000PROLOG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXT"
    "RACT_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_T"
    "O_REGCLASS\000DBG_VALUE\000REG_SEQUENCE\000COPY\000CALLEND\000CALLSTART"
    "\000i_2_reg_ops__opc_mov__rmem__rmem__\000i_3_reg_ops__opc_and__rmem__r"
    "mem__rmem__\000i_3_reg_ops__opc_or__rmem__rmem__rmem__\000i_3_reg_ops__"
    "opc_sll__rmem__rmem__rmem__\000i_3_reg_ops__opc_sra__rmem__rmem__rmem__"
    "\000i_3_reg_ops__opc_srl__rmem__rmem__rmem__\000i_3_reg_ops__opc_vadd__"
    "rmem__rmem__rmem__\000i_3_reg_ops__opc_vmul__rmem__rmem__rmem__\000i_3_"
    "reg_ops__opc_vsub__rmem__rmem__rmem__\000i_3_reg_ops__opc_xor__rmem__rm"
    "em__rmem__\000i_arithm_imm__opc_addi__rmem__rmem__uimm16__\000i_arithm_"
    "imm__opc_addi__rmem__rmem__uimm16____SPEC_op0_0\000i_arithm_imm__opc_or"
    "i__rmem__rmem__uimm16__\000i_arithm_imm__opc_ori__rmem__rmem__uimm16___"
    "_SPEC_op0_0\000i_arithm_imm__opc_ori__rmem__rmem__uimm16____SPEC_op0_65"
    "535\000i_ext__opc_sext32__rmem__rmem__\000i_ext__opc_sext8__rmem__rmem_"
    "_\000i_ext__opc_zext16__rmem__rmem__\000i_ext__opc_zext8__rmem__rmem__\000"
    "i_jump_call_imm__opc_call_imm__address26__ES_\000i_jump_call_imm__opc_c"
    "all_imm__address26__GA_\000i_jump_call_imm__opc_jump_imm__address26__\000"
    "i_jump_call_reg__opc_call_reg__rmem__\000i_jump_call_reg__opc_jump_reg_"
    "_rmem__\000i_jump_call_reg__opc_jump_reg__rmem___RETURN_CLONE_\000i_jum"
    "p_cond__opc_jumpeq__rmem__rmem__simm16_rel__\000i_jump_cond__opc_jumpne"
    "q__rmem__rmem__simm16_rel__\000i_load_store__opc_load__rmem__rmem__simm"
    "16__\000i_load_store__opc_load__rmem__rmem__simm16____SPEC_op0_0\000i_l"
    "oad_store__opc_store__rmem__rmem__simm16__\000i_load_store__opc_store__"
    "rmem__rmem__simm16____SPEC_op0_0\000i_movhi__opc_movhi__rmem__uimm16__\000"
    "i_movhi__opc_movhi__rmem__uimm16____SPEC_op0_0\000";
  return Strs+InstAsmOffset[Opcode];
}

#endif
