clsCircuit Class Reference

object of the class represents in-circuit circuit More...

#include <model.h>

Public Member Functions
	clsCircuit (string nm)
	constructor
	~clsCircuit ()
	destructor
bool	operator< (clsCircuit const &c) const
	definition of the '<' operator over class objects
bool	operator!= (clsCircuit c) const
	definition of the '!=' operator over class objects
bool	operator* (clsCircuit const &c) const
	definition of the '*' operator over class objects
string	getName () const
	gets circuit name
int	getNAllBits ()
	gets sum of bits within in-design interfaces
int	getNBits ()
	gets sum of bits with data-flow control ability within in-design interfaces
int	getNClks ()
	gets sum of clock-bits within in-design interfaces
bool	addPort (string nm, int nt, int w, bool orig=true)
	adds a port with specified width to circuit interface
clsPort *	findPort (string nm)
	searches for a port to be stored in clsCircui::mapPort
map< string, clsPort >::iterator	getMapPortBegin ()
	gets begining of clsCircuit::mapPort
map< string, clsPort >::iterator	getMapPortEnd ()
	gets end of clsCircuit::mapPort
int	getNallPorts ()
	gets sum of bits within in-design interfaces
double	getAvgPortWidth ()
	gets average width of ports within the circuit
bool	addMod (string nm, string t, bool orig=true)
	adds module of specified type to the circuit
clsModule *	findMod (string nm)
	searches for a module to be stored in clsCircuit::mapMod
map< string, clsModule >::iterator	getMapModBegin ()
	gets begining of clsCircuit::mapMod
map< string, clsModule >::iterator	getMapModEnd ()
	gets end of clsCircuit::mapMod
int	getNmodules () const
	gets number of in-circuit modules
bool	addWire (clsWire w)
	adds a wire to clsCircuit::setOfWires
bool	connectPorts (string sm, string sp, string dm, string dp, bool reverse, bool orig=true)
	connects two interfaces at the circuit-level
set< clsWire >::iterator	getSetOfWiresBegin ()
	gets begining of clsCircuit::setOfWires
set< clsWire >::iterator	getSetOfWiresEnd ()
	gets end of clsCircuit::setOfWires
void	eraseWire (set< clsWire >::iterator w)
	erases data stored in clsCircuit::setOfWires
int	getNwires () const
	gets number of in-circuit wires
void	evalArea ()
	estimates area of the circuit
int	getArea ()
	returns estimation of circuit area
void	evalPower ()
	estimates peak power-consumption of the circuit
int	getPower ()
	returns estimation of peak power consumption of the circuit
int	controlability_analysis (set< string > *marked_bits)
	starts controllability analysis
int	observability_analysis (set< string > *marked_bits)
	starts observability analysis
int	testability_analysis ()
	starts testability analysis (controllability analysis first and observability analysis afterwards)
void	evalTst ()
	according to testability analysis results, it completes evaluation of testability parameters of all in-circuit ports and circuit itself
set< string >	get_untestableBits (tmodeSel mode)
	gets set of uncontrollable/unobservable/untestable bits within the circuit
set< string >	get_badTsourceBits (int type)
	not implemented yet
set< string >	get_regNames (string fname)
	gets register names specified in special file (see tool's command-line help)
set< string >	get_scanRegCandidateBits (set< string > regs)
	returns set of in-register bits as candidates for selection into scan chains
set< string >	get_scanRegCandidates (set< string > regs)
	returns set of registers as candidates for selection into scan chains
void	export_TAresults_txt (string fname)
	exports testability analysis results to a plain-text formated file (see help to tool's command-line option -o)
void	export_TAresults_htm (string fname)
	exports testability analysis results to a html-formated file (see help to tool's command-line option -o)
void	export_TAresults_tex (string fname)
	exports testability analysis results to a LaTEX-formated file (see help to tool's command-line option -o)
set< string >	get_scan_notation (string fname)
	gets scan notation from a file (see help to tool's command-line option -scan)
bool	implement_scan_notation (string fsname, string frname)
	implements scan notation into circuit structure
bool	deimplement_changes ()
	returns circuit structure into its original state
void	implementDft ()
	used to implement all requested design-for-testability technique(s) in the future. Actually, only clsCircuit::implement_scan_notation is called in the function
Data Fields
double	con
	controllability value of the circuit
double	obs
	observability value of the circuit
double	tst
	testability value of the circuit
double	rcon
	ratio of controllable nodes within the circuit
double	robs
	ratio of observable nodes within the circuit
double	rtst
	ratio of testable nodes within the circuit
Private Attributes
string	name
	circuit name
map< string, clsPort >	mapPort
	map of in-circuit ports
map< string, clsModule >	mapMod
	map of in-circuit modules
set< clsWire >	setOfWires
	set of in-circuit wires used to decribe interconnections among module interfaces
int	area
	estimated worst-case area value (for update, call clsCircuit::getArea) of the circuit
int	power
	estimated power-consumption value (for update, call clsCircuit::getPower) of the circuit

---

Detailed Description

object of the class represents in-circuit circuit

in the object, information about in-circuit modules, ports, wires etc. is stored. Actually, it is read from circuit-related file specified by means of tool's command line parameters (see tool's help to -i command line parameter). In the next (hierarchical) version of the tool, each module within a circuit can represent another circuit - loaded from a file explicitly specified for such a module. Map of 0-level circuits is in clsDesign::mapCir.

---

Constructor & Destructor Documentation

clsCircuit::clsCircuit

(

string

nm

)

constructor

clsCircuit::~clsCircuit

(

)

destructor

---

Member Function Documentation

bool clsCircuit::operator<

(

clsCircuit const &

c

)

const [inline]

definition of the '<' operator over class objects

bool clsCircuit::operator!=

(

clsCircuit

c

)

const [inline]

definition of the '!=' operator over class objects

bool clsCircuit::operator*

(

clsCircuit const &

c

)

const [inline]

definition of the '*' operator over class objects

string clsCircuit::getName

(

)

const [inline]

gets circuit name

int clsCircuit::getNAllBits

(

)

gets sum of bits within in-design interfaces

int clsCircuit::getNBits

(

)

gets sum of bits with data-flow control ability within in-design interfaces

int clsCircuit::getNClks

(

)

gets sum of clock-bits within in-design interfaces

bool clsCircuit::addPort	(	string	nm,
		int	nt,
		int	w,
		bool	orig = true
	)

adds a port with specified width to circuit interface

Parameters:

[in]	nm	port name
[in]	nt	port type (see tNode)
[in]	w	port width
[in]	orig	port originality flag (set implicitly to true for all original ports)

clsPort* clsCircuit::findPort

(

string

nm

)

[inline]

searches for a port to be stored in clsCircui::mapPort

map<string, clsPort>::iterator clsCircuit::getMapPortBegin

(

)

[inline]

gets begining of clsCircuit::mapPort

map<string, clsPort>::iterator clsCircuit::getMapPortEnd

(

)

[inline]

gets end of clsCircuit::mapPort

int clsCircuit::getNallPorts

(

)

gets sum of bits within in-design interfaces

double clsCircuit::getAvgPortWidth

(

)

gets average width of ports within the circuit

bool clsCircuit::addMod	(	string	nm,
		string	t,
		bool	orig = true
	)

adds module of specified type to the circuit

Parameters:

[in]	nm	module name
[in]	t	module type
[in]	orig	module originality flag (set implicitly to true for all original modules)

clsModule* clsCircuit::findMod

(

string

nm

)

[inline]

searches for a module to be stored in clsCircuit::mapMod

map<string, clsModule>::iterator clsCircuit::getMapModBegin

(

)

[inline]

gets begining of clsCircuit::mapMod

map<string, clsModule>::iterator clsCircuit::getMapModEnd

(

)

[inline]

gets end of clsCircuit::mapMod

int clsCircuit::getNmodules

(

)

const [inline]

gets number of in-circuit modules

bool clsCircuit::addWire

(

clsWire

w

)

adds a wire to clsCircuit::setOfWires

bool clsCircuit::connectPorts	(	string	sm,
		string	sp,
		string	dm,
		string	dp,
		bool	reverse,
		bool	orig = true
	)

connects two interfaces at the circuit-level

Parameters:

[in]	sm	name of source module
[in]	sp	name of source port (belonging to the source module)
[in]	dm	name of destination module
[in]	dp	name of destination port (belonging to the destination module)
[in]	reverse	reversability flag (false to connect ports in given direction, true to connoect them in the oposit direction)
[in]	orig	connection originality flag (set implicitly to true for all original interconnections)

set<clsWire>::iterator clsCircuit::getSetOfWiresBegin

(

)

[inline]

gets begining of clsCircuit::setOfWires

set<clsWire>::iterator clsCircuit::getSetOfWiresEnd

(

)

[inline]

gets end of clsCircuit::setOfWires

void clsCircuit::eraseWire

(

set< clsWire >::iterator

w

)

[inline]

erases data stored in clsCircuit::setOfWires

int clsCircuit::getNwires

(

)

const [inline]

gets number of in-circuit wires

void clsCircuit::evalArea

(

)

[inline]

estimates area of the circuit

int clsCircuit::getArea

(

)

[inline]

returns estimation of circuit area

void clsCircuit::evalPower

(

)

[inline]

estimates peak power-consumption of the circuit

int clsCircuit::getPower

(

)

[inline]

returns estimation of peak power consumption of the circuit

int clsCircuit::controlability_analysis

(

set< string > *

marked_bits

)

starts controllability analysis

Parameters:

[out]

marked_bits

set of bits with controllability marks assigned

int clsCircuit::observability_analysis

(

set< string > *

marked_Cbits

)

starts observability analysis

Warning:

before the analysis is started, clsCircuit::controlability_analysis must be finished

Parameters:

[in]

marked_Cbits

set of bits with controllability marks assigned

int clsCircuit::testability_analysis

(

)

starts testability analysis (controllability analysis first and observability analysis afterwards)

void clsCircuit::evalTst

(

)

according to testability analysis results, it completes evaluation of testability parameters of all in-circuit ports and circuit itself

Warning:

return value valid only if testability analysis was run before call of the function

set< string > clsCircuit::get_untestableBits

(

tmodeSel

mode

)

gets set of uncontrollable/unobservable/untestable bits within the circuit

Warning:

return value valid only if testability analysis was run before call of the function

set< string > clsCircuit::get_badTsourceBits

(

int

type

)

not implemented yet

Warning:

return value valid only if testability analysis was run before call of the function

set< string > clsCircuit::get_regNames

(

string

fname

)

gets register names specified in special file (see tool's command-line help)

set< string > clsCircuit::get_scanRegCandidateBits

(

set< string >

regs

)

returns set of in-register bits as candidates for selection into scan chains

set< string > clsCircuit::get_scanRegCandidates

(

set< string >

regs

)

returns set of registers as candidates for selection into scan chains

void clsCircuit::export_TAresults_txt

(

string

fname

)

exports testability analysis results to a plain-text formated file (see help to tool's command-line option -o)

Warning:

return value valid only if testability analysis was run before call of the function

void clsCircuit::export_TAresults_htm

(

string

fname

)

exports testability analysis results to a html-formated file (see help to tool's command-line option -o)

Warning:

return value valid only if testability analysis was run before call of the function

void clsCircuit::export_TAresults_tex

(

string

fname

)

exports testability analysis results to a LaTEX-formated file (see help to tool's command-line option -o)

Warning:

return value valid only if testability analysis was run before call of the function

set< string > clsCircuit::get_scan_notation

(

string

fname

)

gets scan notation from a file (see help to tool's command-line option -scan)

bool clsCircuit::implement_scan_notation	(	string	fsname,
		string	frname
	)

implements scan notation into circuit structure

Parameters:

[in]	fsname	name of a file containing scan-related information
[in]	frname	name of a file containing names of registers within circuit/design

bool clsCircuit::deimplement_changes

(

)

returns circuit structure into its original state

void clsCircuit::implementDft

(

)

used to implement all requested design-for-testability technique(s) in the future. Actually, only clsCircuit::implement_scan_notation is called in the function

---

Field Documentation

string clsCircuit::name [private]

circuit name

map<string, clsPort> clsCircuit::mapPort [private]

map of in-circuit ports

map<string, clsModule> clsCircuit::mapMod [private]

map of in-circuit modules

set<clsWire> clsCircuit::setOfWires [private]

set of in-circuit wires used to decribe interconnections among module interfaces

int clsCircuit::area [private]

estimated worst-case area value (for update, call clsCircuit::getArea) of the circuit

int clsCircuit::power [private]

estimated power-consumption value (for update, call clsCircuit::getPower) of the circuit

double clsCircuit::con

controllability value of the circuit

Warning:

value valid only if testability analysis was run before reading the value

double clsCircuit::obs

observability value of the circuit

Warning:

value valid only if testability analysis was run before reading the value

double clsCircuit::tst

testability value of the circuit

Warning:

value valid only if testability analysis was run before reading the value

double clsCircuit::rcon

ratio of controllable nodes within the circuit

Warning:

return value valid only if testability analysis was run before reading the value

double clsCircuit::robs

ratio of observable nodes within the circuit

Warning:

return value valid only if testability analysis was run before reading the value

double clsCircuit::rtst

ratio of testable nodes within the circuit

Warning:

return value valid only if testability analysis was run before reading the value

---

The documentation for this class was generated from the following files:

• model.h
• model.cc