// Begin

// Modified NL1 circuit (NL4)
// Modification: R2 modified to scan (modification done at netlist level)

// Circuit name and interface
CIR NestedLoops In(in,4) clk(clk,1) Out(out,4) s_in(in,1) s_out(out,1) mode(in,1)

// Module names and types
ITM FU1(ADD_4a) 
ITM FU2(ADD_4a) 
ITM FU3(MUL_4_8comb) 
ITM R1(REG_4) 
ITM R2(SREG_4) 
ITM R3(REG_4) 

// List of interconnections
// If no bijection given, it's supposed to be an identity
LINK NestedLoops.In(0:3) -> FU1.x(0:3)
LINK NestedLoops.clk -> R1.clk
LINK NestedLoops.clk -> R2.clk
LINK NestedLoops.clk -> R3.clk
LINK NestedLoops.s_in -> R2.s_in
LINK NestedLoops.mode -> R2.mode
LINK R2.s_out -> NestedLoops.s_out
LINK FU1.s -> R1.d
LINK R1.y -> FU2.x
LINK FU2.s -> R2.d
LINK R2.y -> FU3.x
LINK FU3.m(7:4) -> R3.d
LINK R3.y -> FU1.y FU2.y FU3.y NestedLoops.Out

// End
