// Begin

// Modified NL1 circuit (NL2)
// Modification: MX1 inserted into most-nested loop

// Circuit name and interface
CIR NestedLoops2 In(in,4) dx(in,4) sel(sel,1) clk(clk,1) Out(out,4)

// Module names and types
ITM FU1(ADD_4a)
ITM FU2(ADD_4a)
ITM FU3(ADD_4a)
ITM R1(REG_4) 
ITM R2(REG_4) 
ITM R3(REG_4) 
ITM MX1(MUX_4)

// List of interconnections
// If no bijection given, it's supposed to be an identity
LINK NestedLoops2.In -> FU1.x
LINK NestedLoops2.dx -> MX1.b
LINK NestedLoops2.sel -> MX1.sel
LINK NestedLoops2.clk -> R1.clk
LINK NestedLoops2.clk -> R2.clk
LINK NestedLoops2.clk -> R3.clk
LINK FU1.s -> R1.d
LINK R1.y -> FU2.x
LINK FU2.s -> R2.d
LINK R2.y -> FU3.x
LINK FU3.s -> MX1.a
LINK MX1.y -> R3.d
LINK R3.y -> FU1.y FU2.y FU3.y NestedLoops2.Out

// End
