Publication Details
Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description
automatic formal verification, correspondence checking, ISA, microprocessor,
instruction, RTL, bounded model checking
The paper proposes an automated approach with a formal basis designed for
checking correspondence between an RTL implementation of a microprocessor and
a description of its instruction set architecture (ISA). The goals of the
approach are to find bugs not discovered by functional verification, to minimize
user intervention in the verification process, and to provide a developer with
practical results within a short period of time. The main idea is to use bounded
model checking to check that the output produced by automatically derived RTL and
ISA models of a given processor are the same for each instruction and each
possible input. Although the approach does not provide full formal verification,
experiments with the approach confirm that due to a different way it explores the
state space of the design under test, it can find bugs not found by functional
verification, and is thus a useful complement to functional verification.
@inproceedings{BUT97556,
author="Lukáš {Charvát} and Aleš {Smrčka} and Tomáš {Vojnar}",
title="Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description",
booktitle="Proceedings of the 13th International Workshop on Microprocessor Test and Verification (MTV 2012)",
year="2012",
pages="6--12",
publisher="Institute of Electrical and Electronics Engineers",
address="Austin, TX",
doi="10.1109/MTV.2012.19",
isbn="978-1-4673-4441-8",
url="http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6519727"
}