Publication Details
Reducing memory in high-speed packet classification
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
FPGA, SRAM, hardware, parallelism, classification
Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.
@inproceedings{BUT97051,
author="Viktor {Puš} and Jan {Kořenek}",
title="Reducing memory in high-speed packet classification",
booktitle="Proceedings of the 8th International Wireless Communications and Mobile Computing Conference",
year="2012",
pages="437--442",
publisher="Frederick University",
address="Limassol",
isbn="978-1-4577-1377-4",
url="https://www.fit.vut.cz/research/publication/10167/"
}