Publication Details

Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering

SEKANINA, L.; SALAJKA, V.; VAŠÍČEK, Z. Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering. In 2012 IEEE World Congress on Computational Intelligence. CA: Institute of Electrical and Electronics Engineers, 2012. p. 432-439. ISBN: 978-1-4673-1508-1.
Czech title
Dvoukroková evoluce polymorfních obvodů pro filtraci obrazu
Type
conference paper
Language
English
Authors
Keywords

image filter, multifunctional logic, genetic programming, digital circuit

Abstract



This paper proposes to implement multifunctional image filters using
multifunctional gates such as polymorphic gates or multiplexed ordinary gates.
The design procedure is based on evolutionary design and optimization conducted
using Cartesian genetic programming (CGP). Because of the complexity of the
problem the design is decomposed to two phases. In the first step,
a multifunctional filter is evolved at the register-transfer level (RTL) using
a set of processing elements containing functions such as minimum/maximum,
minimum/average etc. over two pixels. In the second step, gate-level
implementations of the processing elements utilized in evolved filters are
designed and optimized using CGP in combination with conventional logic synthesis
tools. It is shown that resulting filters exhibit good filtering capabilities.
They are also area-efficient in comparison with solutions based on multiplexing
of ordinary filters.  

Published
2012
Pages
432–439
Proceedings
2012 IEEE World Congress on Computational Intelligence
Conference
IEEE World Congress on Computational Intelligence, Brisbane, AU
ISBN
978-1-4673-1508-1
Publisher
Institute of Electrical and Electronics Engineers
Place
CA
DOI
UT WoS
000312859301090
EID Scopus
BibTeX
@inproceedings{BUT96889,
  author="Lukáš {Sekanina} and Vojtěch {Salajka} and Zdeněk {Vašíček}",
  title="Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering",
  booktitle="2012 IEEE World Congress on Computational Intelligence",
  year="2012",
  pages="432--439",
  publisher="Institute of Electrical and Electronics Engineers",
  address="CA",
  doi="10.1109/CEC.2012.6256164",
  isbn="978-1-4673-1508-1",
  url="https://www.fit.vut.cz/research/publication/9865/"
}
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