Publication Details

Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

KOŠAŘ, V.; KOŘENEK, J. Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 401-402. ISBN: 978-1-4244-9753-9.
Czech title
Redukce zabraných zdrojů FPGA pro vyhledávání vzorů popsaných regulárními výrazy pomocí relace podobnosti
Type
conference paper
Language
English
Authors
Košař Vlastimil, Ing., Ph.D. (DCSY)
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Keywords

FPGA, NFA, reduction, regular expression matching

Abstract

Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.

Published
2011
Pages
401–402
Proceedings
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus
BibTeX 
@inproceedings{BUT76456,
  author="Vlastimil {Košař} and Jan {Kořenek}",
  title="Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="401--402",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9",
  url="https://www.fit.vut.cz/research/publication/9766/"
}
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