Publication Details
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
Otero Andres
Mora Javier
De la Torre Eduardo
Riesgo Teresa
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
field programmable gate array, dynamic partial reconfiguration, image filter,
evolvable hardware
This paper addresses the modelling and validation of an evolvable hardware
architecture which can be mapped
on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The
adaptation capabilities of the
architecture are exercised to validate its evolvability. The underlying proposal
is the use of a library of reconfigurable
components characterised by their partial bitstreams, which are used by the
Evolutionary Algorithm to find a solution
to a given task. Evolution of image noise filters is selected as the proof of
concept application. Results show that
computation speed of the resulting evolved circuit is higher than with the
Virtual Reconfigurable Circuits approach, and
this can be exploited on the evolution process by using dynamic reconfiguration.
@inproceedings{BUT76400,
author="Ruben {Salvador} and Andres {Otero} and Javier {Mora} and Eduardo {De la Torre} and Teresa {Riesgo} and Lukáš {Sekanina}",
title="Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support",
booktitle="Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems",
year="2011",
pages="184--191",
publisher="IEEE Computer Society",
address="Los Alamitos",
isbn="978-1-4577-0599-1",
url="https://www.fit.vut.cz/research/publication/9682/"
}