SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

SEU, simulatotion, generator, framework, online testing, fault tolerance

In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.