Publication Details
Retargetable Multi-level Debugging in HW/SW Codesign
Přikryl Zdeněk, Ing., Ph.D.
Kolář Dušan, doc. Dr. Ing. (DIFS)
Hruška Tomáš, prof. Ing., CSc. (DIFS)
debugging; breakpoint; simulation; DWARF; JTAG; architecture description
languages; application-specific instruction set processors
Debugging is a standard part of an embedded system design process. The debugger
is used for a target application debugging and for a testing of the designed
system. The target application debugging can be performed either on
a statement-accurate level (i.e. source-language level debugging) or on an
instruction-accurate level (i.e. assembly-language level debugging). The
architecture design debugging is done on a cycle-accurate level. Nowadays
embedded systems are often parallel-based. Therefore, it is important to allow
debugging of systems with more than one application-specific instruction set
processors (ASIP). Since the current trend of ASIP design is focused on automatic
tool-chain generation, the debugger must be retargetable to arbitrary
architecture. In this paper, we present the concept of an automatically generated
multi-level retargetable debugger. This debugger can operate on each of the
previously mentioned levels and it allows debugging of multiprocessor systems.
The experimental results can be found at the end of the paper.
@inproceedings{BUT76308,
author="Jakub {Křoustek} and Zdeněk {Přikryl} and Dušan {Kolář} and Tomáš {Hruška}",
title="Retargetable Multi-level Debugging in HW/SW Codesign",
booktitle="The 23rd International Conference on Microelectronics (ICM 2011)",
year="2011",
pages="1--6",
publisher="Institute of Electrical and Electronics Engineers",
address="Hammamet",
doi="10.1109/ICM.2011.6177413",
isbn="978-1-4577-2209-7",
url="https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6177413"
}