Publication Details

A Global Postsynthesis Optimization Method for Combinational Circuits

VAŠÍČEK, Z.; SEKANINA, L. A Global Postsynthesis Optimization Method for Combinational Circuits. Proc. of the Design, Automation and Test in Europe DATE 2011. Grenoble: European Design and Automation Association, 2011. p. 1525-1528. ISBN: 978-3-9810801-7-9.
Czech title
Metoda pro globální post-syntézní optimalizaci kombinačních obvodů
Type
conference paper
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
URL
Keywords

logic synthesis, genetic programming, SAT solver

Abstract

A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.

Published
2011
Pages
1525–1528
Proceedings
Proc. of the Design, Automation and Test in Europe DATE 2011
ISBN
978-3-9810801-7-9
Publisher
European Design and Automation Association
Place
Grenoble
BibTeX 
@inproceedings{BUT76297,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="A Global Postsynthesis Optimization Method for Combinational Circuits",
  booktitle="Proc. of the Design, Automation and Test in Europe DATE 2011",
  year="2011",
  pages="1525--1528",
  publisher="European Design and Automation Association",
  address="Grenoble",
  isbn="978-3-9810801-7-9",
  url="https://www.fit.vut.cz/research/publication/9521/"
}
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