Publication Details

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL, J. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, 2006, vol. 25, no. 5, p. 441-464. ISSN: 1335-9150.

Czech title

Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů

Type

journal article

Language

English

Authors

Strnadel Josef, Ing., Ph.D. (DCSY)

URL

Keywords

digital circuit, testing, register-transfer level, data-path, testability analysis, design for testability, scan technique

Abstract

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

Published

2006

Pages

441–464

Journal

Computing and Informatics, vol. 25, no. 5, ISSN 1335-9150

BibTeX

@article{BUT45082,
  author="Josef {Strnadel}",
  title="Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
  journal="Computing and Informatics",
  year="2006",
  volume="25",
  number="5",
  pages="441--464",
  issn="1335-9150"
}