Publication Details

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

KAŠTIL, J.; KOŘENEK, J. Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010. p. 149-152. ISBN: 978-1-4244-6610-8.
Czech title
Hardwarově akcelerované vyhledávání vzorů založené na deterministickém konečném automatu s perfektním hašováním
Type
conference paper
Language
English
Authors
Kaštil Jan, Ing., Ph.D.
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Keywords

Intrusion Detection, Perfect Hashing,hardware acceleration, Deterministic Finite Automata

Abstract

With the increased amount of data transferred by computer networks, the amount of the malicious traffic also increases and therefore it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. Pattern matching is the time critical operation of current IDS. This paper deals with the analysis of regular expressions used by modern IDS to describe malicious traffic. According to our analysis, more than 64 percent of regular expressions create Deterministic Finite Automaton (DFA) with less than 20 percent of saturation of the transition table which allows efficient implementation of pattern matching into FPGA platform. We propose architecture for fast pattern matching using perfect hashing suitable for implementation into FPGA platform. The memory requirements of presented architecture is closed to the theoretical minimum for sparse transition tables.

Annotation

With the increased amount of data transferred by
computer networks, the amount of the malicious traffic also
increases and therefore it is necessary to protect networks
by security systems such as firewalls and Intrusion Detection
Systems (IDS) operating at multigigabit speeds. Pattern matching
is the time critical operation of current IDS. This paper deals
with the analysis of regular expressions used by modern IDS
to describe malicious traffic. According to our analysis, more
than 64 percent of regular expressions create Deterministic Finite
Automaton (DFA) with less than 20 percent of saturation of
the transition table which allows efficient implementation of
pattern matching into FPGA platform. We propose architecture
for fast pattern matching using perfect hashing suitable for
implementation into FPGA platform. The memory requirements
of presented architecture is closed to the theoretical minimum
for sparse transition tables.

Published
2010
Pages
149–152
Proceedings
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
ISBN
978-1-4244-6610-8
Publisher
IEEE Computer Society
Place
Vienna
BibTeX 
@inproceedings{BUT35426,
  author="Jan {Kaštil} and Jan {Kořenek}",
  title="Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing",
  booktitle="Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010",
  year="2010",
  pages="149--152",
  publisher="IEEE Computer Society",
  address="Vienna",
  isbn="978-1-4244-6610-8",
  url="https://www.fit.vut.cz/research/publication/9200/"
}
Back to top