Publication Details
Design and Debugging of Parallel Architectures Using the ISAC Language
Křoustek Jakub, Ing., Ph.D.
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Kolář Dušan, doc. Dr. Ing. (DIFS)
Masařík Karel, Ing., Ph.D. (CM-SDE)
Husár Adam, Ing., Ph.D.
Architecture description language, ISAC, VLIW, multiprocessor system on a chip, simulation, debugging
Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used in multi-processor systems on a chip. Architecture description languages (ADL) are very effective for description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.
@inproceedings{BUT35126,
author="Zdeněk {Přikryl} and Jakub {Křoustek} and Tomáš {Hruška} and Dušan {Kolář} and Karel {Masařík} and Adam {Husár}",
title="Design and Debugging of Parallel Architectures Using the ISAC Language",
booktitle="Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems",
year="2010",
pages="213--221",
publisher="Global Science & Technology Forum",
address="Singapore",
isbn="978-981-08-7656-2"
}