Publication Details
Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints
Židek Stanislav, Ing.
Kolář Dušan, doc. Dr. Ing. (DIFS)
Meduna Alexandr, prof. RNDr., CSc. (DIFS)
scattered context grammar, SCG, VLIW, assembler, conflicts, latency
More and more nowadays data processing System-on-Chip (SoC) devices exploit the
very long instruction word (VLIW) technology. The high performance of VLIW
processors is achieved by a high instruction level parallelism. Program execution
is scheduled statically at compilation time. Therefore, there is no need for
run-time control mechanisms and hardware can be relatively simple. On the other
hand, all constraints checks must be done by the compiler.
This paper describes formal method for modeling instruction level limitations of
these processors. This method is based on scattered context grammars that
generate proper assembler code. This concept has two advantages - formal
description of the dependency checking process and high reduction of description
complexity over other methods.
@inproceedings{BUT34822,
author="Jakub {Křoustek} and Stanislav {Židek} and Dušan {Kolář} and Alexandr {Meduna}",
title="Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints",
booktitle="Proceedings of the 12th Biennial Baltic Electronics Conference",
year="2010",
pages="165--168",
publisher="Institute of Electrical and Electronics Engineers",
address="Tallinn",
doi="10.1109/BEC.2010.5630284",
isbn="978-1-4244-7357-1",
url="https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5630284"
}