Publication Details

Usage of Decompilation in Processor Architecture Modeling

KŘOUSTEK, J. Usage of Decompilation in Processor Architecture Modeling. Proceedings of XXXIth International Autumn Colloquium Advanced Simulation of Systems. Ostrava: 2009. p. 64-67. ISBN: 978-80-86840-47-5.

Czech title

Využití dekompilaci při modelování architektur procesorů

Type

conference paper

Language

English

Authors

Křoustek Jakub, Ing., Ph.D.

Keywords

reverse engineering, decompilation, debugging, Lissom, VLIW

Abstract

This paper explains concept of generic decompiler and its use in processor architecture modeling. Generic decompiler is a tool that can recompile any binary form of program to a chosen high level language representation. Output must be functionally equivalent to the input. Process of decompilation is highly dependent on the processor architecture. This problem is solvable by a special language for description of architecture and instruction semantic. Generic decompiler will be the main part of the planned tool - generic debugger. Special case of usage of such a tool is debugging optimized code for VLIW architectures, due to their complexity. The whole concept will be implemented in practice in project Lissom (FIT BUT). The Lissom project is focused on hardware/software co-design. Generic debugger will be a part of automatically generated tool-set.

Published

2009

Pages

64–67

Proceedings

Proceedings of XXXIth International Autumn Colloquium Advanced Simulation of Systems

ISBN

978-80-86840-47-5

Place

Ostrava

BibTeX

@inproceedings{BUT33749,
  author="Jakub {Křoustek}",
  title="Usage of Decompilation in Processor Architecture Modeling",
  booktitle="Proceedings of XXXIth International Autumn Colloquium Advanced Simulation of Systems",
  year="2009",
  pages="64--67",
  address="Ostrava",
  isbn="978-80-86840-47-5"
}