Publication Details

Verifying VHDL Design with Multiple Clocks in SMV

SMRČKA, A.; ŘEHÁK, V.; VOJNAR, T.; ŠAFRÁNEK, D.; MATOUŠEK, P.; ŘEHÁK, Z. Verifying VHDL Design with Multiple Clocks in SMV. In Formal Methods: Applications and Technology. Lecture Notes in Computer Science. Lecture Notes in Computer Science 4346. Bonn: Springer Verlag, 2007. p. 148-164. ISBN: 978-3-540-70951-0. ISSN: 0302-9743.
Czech title
Verifikace návrhu VHDL s více hodinami v SMV
Type
conference paper
Language
English
Authors
Smrčka Aleš, Ing., Ph.D. (DITS)
Řehák Vojtěch, doc. RNDr.
Vojnar Tomáš, prof. Ing., Ph.D. (DITS)
Šafránek David
Šafránek David, doc. Mgr., Ph.D.
Matoušek Petr, doc. Ing., Ph.D., M.A. (DIFS)
Řehák Zdeněk
URL
Keywords

model checking, hardware, VHDL, multiple clocks, SMV

Abstract

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

Annotation

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, ie. designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

Published
2007
Pages
148–164
Journal
Lecture Notes in Computer Science, vol. 2007, no. 4346, ISSN 0302-9743
Proceedings
Formal Methods: Applications and Technology
Series
Lecture Notes in Computer Science 4346
ISBN
978-3-540-70951-0
Publisher
Springer Verlag
Place
Bonn
BibTeX
@inproceedings{BUT30749,
  author="Aleš {Smrčka} and Vojtěch {Řehák} and Tomáš {Vojnar} and David {Šafránek} and David {Šafránek} and Petr {Matoušek} and Zdeněk {Řehák}",
  title="Verifying VHDL Design with Multiple Clocks in SMV",
  booktitle="Formal Methods: Applications and Technology",
  year="2007",
  series="Lecture Notes in Computer Science 4346",
  journal="Lecture Notes in Computer Science",
  volume="2007",
  number="4346",
  pages="148--164",
  publisher="Springer Verlag",
  address="Bonn",
  isbn="978-3-540-70951-0",
  issn="0302-9743"
}
Back to top