Publication Details

High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

MATOUŠEK, P.; SMRČKA, A.; VOJNAR, T. High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science. Lecture Notes in Computer Science 3725/2005. Berlin: Springer Verlag, 2005. p. 371-375. ISBN: 978-3-540-29105-3. ISSN: 0302-9743.
Czech title
Vysokoúrovňové modelování, analýza a verifikace návrhu hardware založeného na FPGA
Type
conference paper
Language
English
Authors
URL
Keywords

formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks

Abstract

The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.

Published
2005
Pages
371–375
Journal
Lecture Notes in Computer Science, vol. 2005, no. 3725, ISSN 0302-9743
Proceedings
Correct Hardware Design and Verification Methods
Series
Lecture Notes in Computer Science 3725/2005
ISBN
978-3-540-29105-3
Publisher
Springer Verlag
Place
Berlin
BibTeX
@inproceedings{BUT30742,
  author="Petr {Matoušek} and Aleš {Smrčka} and Tomáš {Vojnar}",
  title="High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design",
  booktitle="Correct Hardware Design and Verification Methods",
  year="2005",
  series="Lecture Notes in Computer Science 3725/2005",
  journal="Lecture Notes in Computer Science",
  volume="2005",
  number="3725",
  pages="371--375",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-29105-3",
  issn="0302-9743",
  url="http://www.fit.vutbr.cz/~vojnar/Publications/smv-charme-05.ps.gz"
}
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