Publication Details

Power Conscious RTL Test Scheduling

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Power Conscious RTL Test Scheduling. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008. p. 265-265. ISBN: 978-80-7355-082-0.
Czech title
RTL plánování testu zohledňující příkon
Type
conference paper
Language
English
Authors
Škarvada Jaroslav, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Herrman Tomáš, Ing., Ph.D.
Keywords

RTL test scheduling, power consumption, circuit partitioning, testable blocks

Abstract

In the paper, a methodology for power conscious RTL test scheduling is presented. At first the circuit under analysis (CUA) is mapped into technological library and partitioned. For each partition the sequences of test vectors are generated and if possible also reordered in order to reduce power consumption during the test application. For the test scheduling the Integer Linear Programming (ILP) model is used. The goal of the methodology is to find the test schedule with lowest test application time and with power consumption less than the allowed limit.

Published
2008
Pages
265–265
Proceedings
4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-7355-082-0
Publisher
Masaryk University
Place
Znojmo
BibTeX 
@inproceedings{BUT30718,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Power Conscious RTL Test Scheduling",
  booktitle="4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2008",
  pages="265--265",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-7355-082-0",
  url="https://www.fit.vut.cz/research/publication/8795/"
}
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