Publication Details

Intrusion Detection System Intended for Multigigabit Networks

KOŘENEK, J.; KOBIERSKÝ, P. Intrusion Detection System Intended for Multigigabit Networks. 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems. Krakow: IEEE Computer Society, 2007. p. 361-364. ISBN: 978-1-4244-1161-0.
Czech title
Systém pro detekci narušení počítačové sítě určeny pro multigigabitové sítě
Type
conference paper
Language
English
Authors
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Kobierský Petr, Ing.
Keywords

Traffic Scanner, Snort, IDS, pattern matching

Abstract

Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on Field-Programmable Gate Array (FPGA). Core generator for automatic mapping of IDS rules to FPGA logic was designed to assure fast packet classification and high speed pattern matching. Proposed architecture has been evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6X card theoretical throughput 6.4~Gbps was achieved for all Snort rules. The designed system can be configured by rules described in Snort format using web interface.

Published
2007
Pages
361–364
Proceedings
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4244-1161-0
Publisher
IEEE Computer Society
Place
Krakow
BibTeX 
@inproceedings{BUT28816,
  author="Jan {Kořenek} and Petr {Kobierský}",
  title="Intrusion Detection System Intended for Multigigabit Networks",
  booktitle="2007 IEEE Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="361--364",
  publisher="IEEE Computer Society",
  address="Krakow",
  isbn="978-1-4244-1161-0"
}
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