Publication Details

Novel Hardware Implementation of Adaptive Median Filters

VAŠÍČEK, Z.; SEKANINA, L. Novel Hardware Implementation of Adaptive Median Filters. In Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 110-115. ISBN: 978-1-4244-2276-0.
Czech title
Nová obvodová implementace adaptivního mediánového filtru
Type
conference paper
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Keywords

adaptive median filter, image processing, FPGA,

Abstract

A new FPGA implementation for adaptive median filters is proposed. Adaptive
median filters exhibit better filtering properties than standard median filters;
however, their implementation cost is higher. Proposed architecture was optimized
for throughput allowing 300M pixels to be filtered per second. The best
performance/cost ratio exhibits the adaptive median filter which utilizes
filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%.
In addition to filtering, adaptive median filters can be also used as detectors
of corrupted pixels (detection statistics).

Published
2008
Pages
110–115
Proceedings
Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Conference
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop , Bratislava, SK
ISBN
978-1-4244-2276-0
Publisher
IEEE Computer Society
Place
Bratislava
DOI
10.1109/ddecs.2008.4538766
UT WoS
000256936300023
BibTeX 
@inproceedings{BUT27767,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Novel Hardware Implementation of Adaptive Median Filters",
  booktitle="Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop",
  year="2008",
  pages="110--115",
  publisher="IEEE Computer Society",
  address="Bratislava",
  doi="10.1109/ddecs.2008.4538766",
  isbn="978-1-4244-2276-0",
  url="https://www.fit.vut.cz/research/publication/8604/"
}
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