Publication Details

Testability Analysis Based on Formal Model

HERRMAN, T. Testability Analysis Based on Formal Model. In Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006. p. 243-248. ISBN: 80-8073-598-0.

Czech title

Analýza testovatelnosti založená na formálním modelu

Type

conference paper

Language

English

Authors

Herrman Tomáš, Ing., Ph.D.

Keywords

formal model, RT level, testable block, testability analysis

Abstract

Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.

Published

2006

Pages

243–248

Proceedings

Proceedings of the Sevnth International Scientific Conference ECI 2006

ISBN

80-8073-598-0

Publisher

Faculty of Electrical Engineering and Informatics, University of Technology Košice

Place

Košice

BibTeX

@inproceedings{BUT22268,
  author="Tomáš {Herrman}",
  title="Testability Analysis Based on Formal Model",
  booktitle="Proceedings of the Sevnth International Scientific Conference ECI 2006",
  year="2006",
  pages="243--248",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0"
}