Publication Details

Testability Estimation Based on Controllability and Observability Parameters

PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. In Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. p. 504-514. ISBN: 0-7695-2609-8.
Czech title
Odhad testovatelnosti na základě parametrů řiditelnosti a pozorovatelnosti
Type
conference paper
Language
English
Authors
Pečenka Tomáš, Ing., Ph.D.
Strnadel Josef, Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Keywords

Testability analysis, controllability, observabillity

Abstract

In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The results gained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

Published
2006
Pages
504–514
Proceedings
Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06)
Series
IEEE CS
ISBN
0-7695-2609-8
Publisher
IEEE Computer Society
Place
Cavtat
BibTeX
@inproceedings{BUT22255,
  author="Tomáš {Pečenka} and Josef {Strnadel} and Zdeněk {Kotásek} and Lukáš {Sekanina}",
  title="Testability Estimation Based on Controllability and Observability Parameters",
  booktitle="Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06)",
  year="2006",
  series="IEEE CS",
  pages="504--514",
  publisher="IEEE Computer Society",
  address="Cavtat",
  isbn="0-7695-2609-8"
}
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