Publication Details

Test Scheduling for SOC under Power Constraints

ŠKARVADA, J. Test Scheduling for SOC under Power Constraints. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 91-93. ISBN: 1-4244-0184-4.

Czech title

Plánování testu pro SOC zohledňující příkon energie

Type

conference paper

Language

English

Authors

Škarvada Jaroslav, Ing., Ph.D.

Keywords

test scheduling, power constraint, test application conflict graph, genetic algorithm

Abstract

The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.

Published

2006

Pages

91–93

Proceedings

Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

ISBN

1-4244-0184-4

Publisher

Czech Technical University Publishing House

Place

Prague

BibTeX

@inproceedings{BUT22187,
  author="Jaroslav {Škarvada}",
  title="Test Scheduling for SOC under Power Constraints",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2006",
  pages="91--93",
  publisher="Czech Technical University Publishing House",
  address="Prague",
  isbn="1-4244-0184-4"
}