Publication Details

Speeding-up OAS and AAS Communication in Networking System on Chips

JAROŠ, J.; DVOŘÁK, V. Speeding-up OAS and AAS Communication in Networking System on Chips. Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Sopron: University of West Hungary, 2005. p. 206-209. ISBN: 9639364487.

Czech title

Type

conference paper

Language

English

Authors

Jaroš Jiří, doc. Ing., Ph.D. (DCSY)
Dvořák Václav, prof. Ing., DrSc.

Keywords

BOA algorithm, communication patterns, multiprocessor topology, hypercube, AMP

Abstract

As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.

Published

2005

Pages

206–209

Proceedings

Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems

ISBN

9639364487

Publisher

University of West Hungary

Place

Sopron

BibTeX

@inproceedings{BUT21469,
  author="Jiří {Jaroš} and Václav {Dvořák}",
  title="Speeding-up OAS and AAS Communication in Networking System on Chips",
  booktitle="Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems",
  year="2005",
  pages="206--209",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="9639364487"
}