Control Flow Analysis for Bottom-up Portable Models Creation

PSS, portable stimuli, portable models, simulation-based verification

Portable Test and Stimulus Standard (PSS) is a game-changing standard in the simulation-based verification. This paper focuses on creating a top-level PSS model of the design under verification (DUV) using PSS models of its components (submodels). This is one of the most challenging problems the PSS is currently facing, and it is called vertical reuse of portable models. The hardest part is to create proper constraints for the interconnection of submodels to represent behaviour intended to be verified. This paper aims to evaluate a hypothesis that with the analysis of the control flow inside the DUV, we can significantly simplify the reusability of PSS models in the vertical direction. We believe that the control flow analysis will provide valuable information for creating constraints, as the control signals influence the DUV's behaviour the most. As the DUV, we selected the execution stage subsystem of the PULP platform processor. Firstly, we have created PSS models for all components inside this subsystem. Then we traced the control signals of all these components and created a map of dependencies from the subsystem point of view. Afterwards, we used this analysis to create constraints for the component-level PSS models while interconnecting them to the top-level PSS model.