Publication Details
Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs
Pánek Richard, Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Fault-Tolerant System Design, Electronic Design Automation, Dynamic Partial
Reconfiguration, Redundancy Allocation and Insertion, FPGA, VHDL
This article presents a new design automation method for Fault-Tolerant (FT)
systems implemented on dynamically reconfigurable Field Programmable Gate Arrays
(FPGAs). The method aims at minimizing the human interactions needed to
incorporate FT mechanisms into an existing system. It starts with a source code
of an original unhardened circuit. It continues by automated manipulation of the
source code, algorithmic strategic selection of suitable FT techniques, design
space exploration of candidate FT implementations, and selection of the resulting
implementation. The method also includes efficient evaluation of achieved FT
parameters performed on the target HW. As a novel approach working on the level
of HW description languages is employed, the code modification is separated,
which differentiates our method from others. The case study utilizing this method
targets the design of an experimental FT dynamic partial reconfiguration
controller for an FPGA. This controller is helpful for the restoration of faulty
components due to a single-event upset on an FPGA. We used the method to generate
a set of Pareto-optimal controllers concerning the design's Mean Time to Failure
(MTTF) parameter, power consumption, and size. Then, the FT controller is
connected to several benchmark circuits, and the reliability parameters are
evaluated at the entire system level. Our results show that by replacing the
standard reconfigurable controller with our automatically-designed FT controller
for one specific benchmark, the design size increased by 20.1%, and MTTF
increased by 11.7%. However, the efficiency is highly dependent on the target
system size, MTTF, and circuit functionality. We also estimate that a complex
system defined by half a million configuration bits would improve MTTF by more
than 50%.
@article{BUT185119,
author="Jakub {Lojda} and Richard {Pánek} and Lukáš {Sekanina} and Zdeněk {Kotásek}",
title="Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs",
journal="Microelectronics Reliability",
year="2023",
volume="2023",
number="144",
pages="1--16",
doi="10.1016/j.microrel.2023.114976",
issn="0026-2714",
url="https://www.sciencedirect.com/science/article/pii/S0026271423000768"
}