Optimizing Packet Classification on FPGA

Packet classification is a crucial time-critical operation for many different networking tasks ranging from switching
or routing to monitoring and security devices like firewalls or
IDS. Accelerated architectures implementing packet classification
must satisfy the ever-growing demand for current high-speed networks. However, packet classification is generally used together
with other packet processing algorithms, which decreases the
available hardware resources on the FPGA chip. The introduction
of the P4 language requires the packet classification to be even
more flexible while maintaining a high throughput with limited
resources. Thus, we need flexible and high-performance architectures to balance processing speed and hardware resources for specific types of rules. DCFL algorithm provides high performance
and flexibility. Therefore, we propose optimizations to the DCFL
algorithm and overall packet processing hardware architecture.
The goal is to maximize the throughput and minimize the resource strain. The main idea of the approach is to analyze
the ruleset, identify some conflicting rules and offload these
rules to other hardware modules. This approach allows us
to process packets faster, even in the worst-case scenarios.
Moreover, we can fit more packet processing into the FPGA and
fine-tune the packet processing architecture to meet a specific
network application's throughput and resource demands. With
the proposed optimizations we can achieve up to a 76 % increase
in the throughput of the packet classification. Alternatively, we
can achieve up to a 37 % decrease in resources needed.