Publication Details
On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits
Pečenka Tomáš, Ing., Ph.D.
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Register-transfer level, synthetic benchmark circuit, testability analysis,
evolutionary algorithm
Use of benchmark designs has become an important part of a process of designing
complex systems. However, existing register-transfer level benchmark suites are
not sufficient for evaluation of new architectures and tools; synthetic benchmark
circuits are an alternative. In the paper, it is demonstrated how evolutionary
techniques can be used to generate synthetic benchmarks covering a wide scale of
testability properties. The generation process is driven by a register-transfer
level testability analysis method and generated benchmarks are stored in
synthesizable VHDL source-code. Results gained by proposed method together with
future research trends are discussed at the end of the paper.
@inproceedings{BUT18046,
author="Josef {Strnadel} and Tomáš {Pečenka} and Lukáš {Sekanina}",
title="On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits",
booktitle="Proceedings of 5th Electronic Circuits and Systems Conference",
year="2005",
pages="107--110",
publisher="Slovak University of Technology in Bratislava",
address="Bratislava",
url="https://www.fit.vut.cz/research/publication/7867/"
}