Publication Details

On the Petri Net Based Test Scheduling

RŮŽIČKA, R. On the Petri Net Based Test Scheduling. Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005. Linz: Johannes Kepler University Linz, 2005. p. 18-19. ISBN: 3-902457-09-0.

Czech title

K plánování testu založeném na Petriho sítích

Type

conference paper

Language

English

Authors

Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)

Keywords

RTL digital circuit testability, test scheduling optimization

Abstract

This paper discusses some problems with test scheduling optimization of register transfer level (RTL) digital circuit design. The Petri net model, previously proposed for testability verification purposes is now used as a base of C/E system which models test application process. To schedule application of test patterns to elements of a circuit under test, possibility of concurrency must be considered firstly. Parallelism during test application process can significantly reduce time of testing. Another advantage of the approach is that all methods are described formally and are proved.

Published

2005

Pages

18–19

Proceedings

Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005

ISBN

3-902457-09-0

Publisher

Johannes Kepler University Linz

Place

Linz

BibTeX

@inproceedings{BUT18034,
  author="Richard {Růžička}",
  title="On the Petri Net Based Test Scheduling",
  booktitle="Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005",
  year="2005",
  pages="18--19",
  publisher="Johannes Kepler University Linz",
  address="Linz",
  isbn="3-902457-09-0"
}