Publication Details
Resynthesis of logic circuits using machine learning and reconvergent paths
Logic optimization, Cartesian Genetic Programming, Evolutionary Resynthesis S.N.
15.03.2022 Doplněno EID Scopus.
Boolean network scoping represents a common approach incorporated in conventional
synthesis tools for maintaining good scalability of the synthesis process.
Recently, an approach to the local resynthesis based on combination of
evolutionary optimization with the principle of Boolean network scoping has been
proposed. Local resynthesis is an iterative process based on the extraction of
smaller sub-circuits from a complex circuit that are optimized locally and
implanted back to the original circuit. The main advantage of the local
resynthesis is that it can mitigate the problem of scalability of representation
which is typical to the evolutionary algorithms as the efficiency of the
evolutionary optimization applied at the global level deteriorates with the
increasing circuit complexity. Unfortunately, the efficiency of local resynthesis
depends on the efficiency of the sub-circuit extraction process. We propose an
alternative method, based on the reconvergent paths. The evaluation is performed
on a set of highly optimized benchmark problems representing various real-world
controllers, logic and arithmetic circuits. The method provides better results
compared to the state-of-the-art logic synthesis tool and evolutionary
optimization techniques operating locally and globally. A substantially higher
number of redundant gates was removed in more than 70% cases, while keeping the
computational effort at the same level. A huge improvement was achieved
especially for the controllers. On average, the proposed method was able to
remove more than 14.3% of gates. The highest achieved gate reduction was more
than 45% of gates.
@inproceedings{BUT175780,
author="Jitka {Kocnová} and Zdeněk {Vašíček}",
title="Resynthesis of logic circuits using machine learning and reconvergent paths",
booktitle="2021 24th Euromicro Conference on Digital System Design (DSD)",
year="2021",
pages="69--76",
publisher="Institute of Electrical and Electronics Engineers",
address="Palermo",
doi="10.1109/DSD53832.2021.00020",
isbn="978-1-6654-2704-3",
url="https://www.fit.vut.cz/research/publication/12490/"
}