Hardware Acceleration in Computer Networks

The speed of network traffic processing is a crucial parameter for most devices
and systems, because any packet drop can cause lower quality of network services,
affect precise monitoring or disallow detection of security threats. General
purpose processors are not able to process all data on high-speed network links.
For 100\,Gbps links, every packet has to be processed in less than 5 ns. Network
devices widely use hardware acceleration to speed up time-critical operations. 
Therefore, this thesis deals with five widely used time-critical operations
together with corresponding hardware architectures, which are able to achieve
wire speed 10, 40 or even 100 Gbps throughput. In particular, the thesis deals
with packet parsing and header fields extraction, longest prefix matching (IP
look-up), packet classification, pattern matching and deep packet inspection. All
these operations are widely used in precise network monitoring systems, network
security devices and also in the infrastructure of data centres. The thesis
introduces how deep pipelines, perfect hashing and pipelined automata can help to
achieve 100\,Gbps throughput and decrease hardware resources. A novel concept is
introduced to accelerate deep packet inspection. The concept provides software
flexibility together with high performance, because fast packet processing is
controlled at the level of flows by software modules. Moreover, proposed concept
and hardware architectures are used in hardware accelerated network security and
monitoring devices, which has been transferred to successful commercial products
and used to monitor and protect CESNET2 academic network.

• pdf korenek-hab.pdf 4 MB