Publication Details

Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis

KOŘENEK, J.; VRÁNA, R. Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. In Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021. IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Vídeň: Institute of Electrical and Electronics Engineers, 2021. p. 115-118. ISBN: 978-1-6654-3595-6.
Czech title
Efektivní akcelerace rozhodovacích stromů pro analýzu šifrovaného síťového provozu
Type
conference paper
Language
English
Authors
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Vrána Roman, Ing.
Keywords

acceleration, network, threat, detection, decision, tree

Abstract

Network traffic analysis and deep packet inspection are time-consuming tasks, which current processors can not handle at 100 Gbps speed. Therefore security systems need fast packet processing with hardware acceleration. With the growing of encrypted network traffic, it is necessary to extend Intrusion Detection Systems (IDSes) and other security tools by new detection methods. Security tools started to use classifiers trained by machine learning techniques based on decision trees. Random Forest, Compact Random Forest and AdaBoost provide excellent result in network traffic analysis. Unfortunately, hardware architectures for these machine learning techniques need high utilisation of on-chip memory and logic resources. Therefore we propose several optimisations of highly pipelined architecture for acceleration of machine learning techniques based on decision trees. The optimisations use the various encoding of a feature vector to reduce hardware resources. Due to the proposed optimisations, it was possible to reduce LUTs by 70.5 % for HTTP brute force attack detection and BRAMs by 50 % for application protocol identification. Both with only negligible impact on classifiers' accuracy. Moreover, proposed optimisations reduce wires and multiplexors in the processing pipeline, positively affecting the proposed architecture's maximal achievable frequency.

Published
2021
Pages
115–118
Proceedings
Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021
Series
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems
ISBN
978-1-6654-3595-6
Publisher
Institute of Electrical and Electronics Engineers
Place
Vídeň
DOI
10.1109/DDECS52668.2021.9417068
UT WoS
000672620200022
EID Scopus
2-s2.0-85105570217
BibTeX 
@inproceedings{BUT168508,
  author="Jan {Kořenek} and Roman {Vrána}",
  title="Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis",
  booktitle="Proceedings - 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2021",
  year="2021",
  series="IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems",
  pages="115--118",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Vídeň",
  doi="10.1109/DDECS52668.2021.9417068",
  isbn="978-1-6654-3595-6",
  url="https://www.fit.vut.cz/research/publication/12439/"
}
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