Publication Details
FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties
Lojda Jakub, Ing., Ph.D. (DCSY)
Kotásek Zdeněk, doc. Ing., CSc.
Field Programmable Gate Arrays (FPGAs) are becoming more popular in various areas. Single Event Upsets (SEUs) are faults caused by charged particle in configuration memory of SRAM-based FPGAs. Such charged particle can cause incorrect behavior of the whole system. This problem is becoming greater if such system operates in environment with increased radiation (e.g. space applications). Lots of techniques to harden FPGAs against faults exist and new ones are under investigation. One of such techniques is called Triple Modular Redundancy (TMR). It is important to evaluate these techniques on a real system with a real FPGA. Evaluation platform based on artificial fault injection and functional verification for testing fault tolerance methodologies is introduced in this paper. Parts of our experimental system are hardened by using TMR and its experimental evaluation is one of the main parts of this paper. We propose experiments with various fault injection strategies (single and multiple faults) and monitor its impact both on electronic and mechanical part of the experimental system.
@inproceedings{BUT168459,
author="Jakub {Podivínský} and Jakub {Lojda} and Zdeněk {Kotásek}",
title="FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties",
booktitle="INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
year="2018",
pages="9--12",
address="Budapešť",
url="https://www.fit.vut.cz/research/publication/11603/"
}