Publication Details
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs
Cabal Jakub, Ing.
Puš Viktor, Ing., Ph.D.
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
FPGA, high throughput processing, parallelization, data bus, Ethernet, wire-speed
As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses.The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400 Gbps, 1 Tbps and even 2 Tbps Ethernet links.
@inproceedings{BUT168140,
author="Lukáš {Kekely} and Jakub {Cabal} and Viktor {Puš} and Jan {Kořenek}",
title="Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs",
booktitle="Proceedings - Euromicro Conference on Digital System Design, DSD 2020",
year="2020",
pages="49--56",
publisher="IEEE Computer Society",
address="Kranj",
doi="10.1109/DSD51259.2020.00020",
isbn="978-1-7281-9535-3",
url="https://www.fit.vut.cz/research/publication/12341/"
}