Publication Details
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock
Pánek Richard, Ing., Ph.D. (DCSY)
Podivínský Jakub, Ing., Ph.D. (UFYZ)
Čekan Ondřej, Ing., Ph.D. (UFYZ)
Krčma Martin, Ing., Ph.D. (UFYZ)
Kotásek Zdeněk, doc. Ing., CSc.
Electronic Lock, Stepper Motor, Fault Tolerance Analysis, Fault Injection, FPGA,
IMEM, DMEM, LUT
In our research, we focus on Fault-Tolerant system design and testing. Recently,
we also studied Fault Tolerance against random and deliberate faults of
electronic smart locks. In our last research, we tested Software-Implemented
Fault Tolerance in the controller of a smart electronic lock. We found out that
the most sensitive part is the Instruction Memory, but also that our hardening
proved to have only negligible effects on the resulting fault tolerance. In this
paper, we extend our experiments and provide further analysis of potential
pitfalls when hardening using SIFT. We found out that added hardness may improve
resilience to faults. But also, the resilience may be instantly worsened by other
factors, such as increased bus traffic. In our research we found out, that our
hardening did not improve the resiliency to faults most likely due to the
increased bus traffic. This means that it is always important to consider the
complete system and also the parts of the system that are easily overlooked.
@inproceedings{BUT168137,
author="Jakub {Lojda} and Richard {Pánek} and Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Zdeněk {Kotásek}",
title="Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock",
booktitle="2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings",
year="2020",
pages="24--28",
publisher="Institute of Electrical and Electronics Engineers",
address="Varna",
doi="10.1109/EWDTS50664.2020.9224878",
isbn="978-1-7281-9899-6",
url="https://www.fit.vut.cz/research/publication/12322/"
}