Approximating Complex Arithmetic Circuits with Guaranteed Worst-Case Relative Error

automated circuit design, approximate circuits, SAT

We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the worst-case relative error, abbreviated as WCRE. WCRE represents an important error metric relevant in many applications including, e.g., approximation of neural network HW architectures. The method integrates SAT-based error evaluation of approximate circuits into a verifiability-driven search algorithm based on Cartesian genetic programming. We implement the method in our framework ADAC that provides various techniques for automated design of arithmetic circuits. Our experimental evaluation shows that, in many cases, the method offers a superior scalability and allows us to construct, within a few hours, high-quality approximations (providing trade-offs between the WCRE and size) for circuits with up to 32-bit operands. As such, it significantly improves the capabilities of ADAC.