Publication Details
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
approximate circuit, genetic programming, convolutional neural network, hardware
accelerator
Approximate circuits have been developed to provide good tradeoffs between power
consumption and quality of service in error resilient applications such as
hardware accelerators of deep neural networks (DNN). In order to accelerate the
approximate circuit design process and to support a fair benchmarking of circuit
approximation methods, libraries of approximate circuits have been introduced.
For example, EvoApprox8b contains hundreds of 8-bit approximate adders and
multipliers. By means of genetic programming we generated an extended version of
the library in which thousands of 8- to 128-bit approximate arithmetic circuits
are included. These circuits form Pareto fronts with respect to several error
metrics, power consumption and other circuit parameters. In our case study we
show how a large set of approximate multipliers can be used to perform
a resilience analysis of a hardware accelerator of ResNet DNN and to select the
most suitable approximate multiplier for a given application. Results are
reported for various instances of the ResNet DNN trained on CIFAR-10 benchmark
problem.
@inproceedings{BUT168115,
author="Vojtěch {Mrázek} and Lukáš {Sekanina} and Zdeněk {Vašíček}",
title="Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks",
booktitle="2nd IEEE International Conference on Artificial Intelligence Circuits and Systems",
year="2020",
pages="243--247",
publisher="Institute of Electrical and Electronics Engineers",
address="Genoa",
doi="10.1109/AICAS48895.2020.9073837",
isbn="978-1-7281-4922-6",
url="https://arxiv.org/abs/2004.10483"
}