Publication Details
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU
Mrázek Vojtěch, Ing., Ph.D. (DCSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
approximate circuits, approximate multipliers, deep neural networks, DNN
accelerator
Energy efficiency of hardware accelerators of deep neural networks (DNN) can be
improved by introducing approximate arithmetic circuits. In order to quantify the
error introduced by using these circuits and avoid the expensive hardware
prototyping, a software emulator of the DNN accelerator is usually executed on
CPU or GPU. However, this emulation is typically two or three orders of magnitude
slower than a software DNN implementation running on CPU or GPU and operating
with standard floating point arithmetic instructions and common DNN libraries.
The reason is that there is no hardware support for approximate arithmetic
operations on common CPUs and GPUs and these operations have to be expensively
emulated. In order to address this issue, we propose an efficient emulation
method for approximate circuits utilized in a given DNN accelerator which is
emulated on GPU. All relevant approximate circuits are implemented as look-up
tables and accessed through a texture memory mechanism of CUDA capable GPUs. We
exploit the fact that the texture memory is optimized for irregular read-only
access and in some GPU architectures is even implemented as a dedicated cache.
This technique allowed us to reduce the inference time of the emulated DNN
accelerator approximately 200 times with respect to an optimized CPU version on
complex DNNs such as ResNet. The proposed approach extends the TensorFlow library
and is available online at https://github.com/ehw-fit/tf-approximate.
@inproceedings{BUT168114,
author="Filip {Vaverka} and Vojtěch {Mrázek} and Zdeněk {Vašíček} and Lukáš {Sekanina}",
title="TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU",
booktitle="2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
year="2020",
pages="294--297",
publisher="Institute of Electrical and Electronics Engineers",
address="Grenoble",
doi="10.23919/DATE48585.2020.9116299",
isbn="978-3-9819263-4-7",
url="https://www.fit.vut.cz/research/publication/12072/"
}