Publication Details
EA-based refactoring of mapped logic circuits
Cartesian Genetic Programming, Resynthesis, Logic optimization
The increasing complexity of the designs and prob-lematic scalability of original
representations led to a shift ininternal representations used in logic
synthesis and optimization. Heterogeneous representations were replaced with
homogeneous intermediate representations. And-inverter graph (AIG) has been
identified as the most promising structure for scalable logic optimization and
many efficient algorithms were implemented on top of it. However, the inability
of AIG to efficiently represent XOR gates together with heuristic nature of logic
optimization algorithms leads to some inefficiency causing that the logic can be
further minimized even after it has been mapped. This paper presents an
optimization technique based on refactoring targeting mapped combinational
circuits. It iteratively selects large cones of logic, optimizes them and returns
them back to the original structure provided that there is an improvement in some
metric.Performance of the method is evaluated on a set of complex academic and
industrial benchmarks. We show that a 9.2%reduction in area can be achieved in
average compared to thehighly optimized results obtained using the academic
state-of-the-art synthesis tool. In average, more than 14% reduction was observed
for arithmetic circuits.
@inproceedings{BUT158068,
author="Jitka {Kocnová} and Zdeněk {Vašíček}",
title="EA-based refactoring of mapped logic circuits",
booktitle="2019 IEEE International Symposium on Circuits and Systems (ISCAS)",
year="2019",
pages="1--5",
publisher="IEEE Computer Society Press",
address="Red Hook, NY",
doi="10.1109/ISCAS.2019.8702084",
isbn="978-1-7281-0397-6",
url="https://www.fit.vut.cz/research/publication/11847/"
}