Publication Details

Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery

SZURMAN, K.; KOTÁSEK, Z. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 32-35. ISBN: 978-1-7281-1756-0.
Czech title
Metody odolnosti proti poruchám se synchronizací stavu pro TMR soft-core procesor a opravu poruchy za jeho běhu
Type
conference paper
Language
English
Authors
Szurman Karel, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

soft-core processor, triple modular redundancy, state synchronization, partial
dynamic reconfiguration, SEU mitigation

Abstract

Triple Modular Redundancy (TMR) applied with various granularity combined with
periodical scrubbing of a configuration memory or with run-time Partial Dynamic
Reconfiguration (PDR) for fault recovery are one of the most preferred Single
Event Upset (SEU) mitigation techniques used by Fault Tolerant Systems (FTS)
implemented into SRAM-based FPGAs. Usage of PDR and TMR allows recovering of FTSs
from all transient SEU faults and offers run-time fault mitigation compared to
scrubbing methods which only correct configuration upsets and are limited by
scrubbing period latency. Reconfigurable TMR architecture may require global
state maintenance after PDR is applied for fault removal. In such situation,
operational state of reconfigured circuit copy needs to be synchronized with
remaining circuit copies which were active during PDR. This paper evaluates
existing synchronization methods for reconfigurable TMR architectures and
soft-core processors; presents our recent research focused on a state
synchronization methodology compared to the state of the art methods and further
investigates strategy for a state synchronization of TMR-protected soft-core
processor neo430.

Published
2019
Pages
32–35
Proceedings
20th IEEE Latin American Test Symposium (LATS 2019)
Conference
IEEE Latin American Test Symposium, Hotel Fundador, Santiago de Chile, CL
ISBN
978-1-7281-1756-0
Publisher
IEEE Computer Society
Place
Santiago
DOI
10.1109/LATW.2019.8704639
UT WoS
000469850000036
EID Scopus
2-s2.0-85065986601
BibTeX 
@inproceedings{BUT156848,
  author="Karel {Szurman} and Zdeněk {Kotásek}",
  title="Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery",
  booktitle="20th IEEE Latin American Test Symposium (LATS 2019)",
  year="2019",
  pages="32--35",
  publisher="IEEE Computer Society",
  address="Santiago",
  doi="10.1109/LATW.2019.8704639",
  isbn="978-1-7281-1756-0",
  url="https://www.fit.vut.cz/research/publication/11879/"
}
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