Publication Details
Automatizace návrhu spolehlivých systémů a její dílčí komponenty
Kotásek Zdeněk, doc. Ing., CSc.
Design Automation, HLS, High-Level Synthesis, Fault Tolerance Estimation, Fault Tolerant System.
Higher level of chip-level integration allows to implement more complex systems, however, it brings a higher risk of fault manifestation. It is possible to minimize the risk by the usage of fault tolerance techniques and fault masking. The higher complexity, however, makes the task of incorporating such techniques a great challenge. The goal of our research is to develop a method to help automate the process of the transformation of a non-dependable system to its fault tolerant version. We focus on an arbitrary level of abstraction. This paper is focusing on two important processes of the automation method: The redundancy insertion and the result evaluation. The main part of the paper is focusing on presentation of the results obtained through the last year of our research.
@inproceedings{BUT155065,
author="Jakub {Lojda} and Zdeněk {Kotásek}",
title="Automatizace návrhu spolehlivých systémů a její dílčí komponenty",
booktitle="Počítačové architektury & diagnostika 2018",
year="2018",
pages="5--8",
publisher="Západočeská univerzita v Plzni",
address="Stachy",
isbn="978-80-261-0814-6",
url="https://www.fit.vut.cz/research/publication/11760/"
}