Publication Details

Mapping of P4 Match Action Tables to FPGA

KEKELY, M.; KOŘENEK, J. Mapping of P4 Match Action Tables to FPGA. In Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017. p. 1-2. ISBN: 978-90-90-30428-1.

Czech title

Mapování P4 vyhledávacích tabulek do FPGA

Type

conference paper

Language

English

Authors

Kekely Michal, Ing.
Kořenek Jan, doc. Ing., Ph.D. (DCSY)

Keywords

P4, FPGA, packet classification, match action tables

Abstract

Current networks are changing very fast. Network administrators needmore flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.

Published

2017

Pages

1–2

Proceedings

Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS

ISBN

978-90-90-30428-1

Publisher

Institute of Electrical and Electronics Engineers

Place

Ghent

DOI

10.23919/FPL.2017.8056768

UT WoS

000426989400013

EID Scopus

2-s2.0-85034425205

BibTeX

@inproceedings{BUT144482,
  author="Michal {Kekely} and Jan {Kořenek}",
  title="Mapping of P4 Match Action Tables to FPGA",
  booktitle="Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS",
  year="2017",
  pages="1--2",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Ghent",
  doi="10.23919/FPL.2017.8056768",
  isbn="978-90-90-30428-1"
}