Publication Details
Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy
Kotásek Zdeněk, doc. Ing., CSc.
Design Automation, HLS, High-Level Synthesis, CatapultC, Fault Tolerance, Fault
Tolerant System
As chip-level integration grows, it is becoming a great challenge to effectively
utilize provided resources, which results in research in the filed of new digital
systems design methodologies. One of these methodologies is the so-called
High-Level Synthesis (HLS), which is often used in combination with Field
Programmable Gate Arrays (FPGAs). The general objective of our research is to
find a method to incorporate Fault Tolerance (FT) design methodologies into these
new techniques of FT design and to automate the process of FT systems design.
First steps towards redundancy insertion and evaluation of the importance of
particular operations are presented in this paper.
@inproceedings{BUT144457,
author="Jakub {Lojda} and Zdeněk {Kotásek}",
title="Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy",
booktitle="Počítačové architektury & diagnostika 2017",
year="2017",
pages="59--62",
publisher="Slovenská technická univerzita v Bratislavě",
address="Smolenice",
isbn="978-80-972784-0-3",
url="https://www.fit.vut.cz/research/publication/11479/"
}