Publication Details

Test scheduling for embedded systems

KOTÁSEK, Z.; MIKA, D.; STRNADEL, J. Test scheduling for embedded systems. Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003. p. 463-467. ISBN: 0-7695-2003-0.

Czech title

Plánování testu pro vestavěné systémy

Type

conference paper

Language

English

Authors

Kotásek Zdeněk, doc. Ing., CSc.
Mika Daniel, Ing., Ph.D.
Strnadel Josef, Ing., Ph.D. (DCSY)

Keywords

TACG, genetic algorithm, embedded systems

Abstract

The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters.

Published

2003

Pages

463–467

Proceedings

Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003

ISBN

0-7695-2003-0

Publisher

IEEE Computer Society Press

Place

Belek

BibTeX

@inproceedings{BUT14193,
  author="Zdeněk {Kotásek} and Daniel {Mika} and Josef {Strnadel}",
  title="Test scheduling for embedded systems",
  booktitle="Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003",
  year="2003",
  pages="463--467",
  publisher="IEEE Computer Society Press",
  address="Belek",
  isbn="0-7695-2003-0"
}